Non-concatenated FEC codes for ultra-high speed optical transport networks

摘要

A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.

主权项

1. A decoder for decoding forward error correcting codewords according to an iterative decoding process using a parity check matrix comprising a plurality of sub-matrices, the decoder comprising:
a plurality of check node processing units, each check node processing performing a check node computation corresponding to a different row of the parity check matrix, the plurality of check node processing units comprising a plurality of pipeline processing stages including:
a first stage including at least a first processing unit to receive and process messages;a second stage following the first stage, the second stage including a message memory to receive the messages from the first processing unit and temporarily store the messages; anda third stage following the second stage, the third stage including a second processing unit to receive the messages from the message memory and further process the messages;wherein at a given time instance, the first processing unit performs a check node computation associated with a second iteration of an iterative decoding algorithm applied to a first codeword, the message memory has stored results from the first processing unit for a first iteration of the iterative decoding algorithm applied to the second codeword, and the second processing unit performs a check node computation associated with a first iteration of the iterative decoding algorithm applied to the first codeword; a plurality of variable node processing units, each variable node processing unit determining variable node update computations corresponding to different columns belonging to a same sub-matrix of the parity check matrix.