| 发明名称 | Test circuit, memory system, and test method of memory system | ||
| 摘要 | This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit. | ||
| 申请公布号 | US8918685(B2) | 申请公布日期 | 2014.12.23 |
| 申请号 | US201213603597 | 申请日期 | 2012.09.05 |
| 申请人 | SK Hynix Inc. | 发明人 | Yang Hyung-Gyun;Lee Hyung-Dong;Kwon Yong-Kee;Moon Young-Suk;Kim Hong-Sik |
| 分类号 | G11C29/00 | 主分类号 | G11C29/00 |
| 代理机构 | IP & T Group LLP | 代理人 | IP & T Group LLP |
| 主权项 | 1. A test circuit comprising: a test execution unit configured to perform a test on a target test memory circuit; an internal storage unit configured to store data for the test execution unit; and a conversion setting unit configured to set a part of or an entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit. | ||
| 地址 | Gyeonggi-do KR | ||