Method and apparatus for filter-less analog input class D audio amplifier clipping

摘要

An integrated circuit (IC) chip has a class D PWM (pulse width modulation) amplifier configured for generating first and second PWM signals. The class-D PWM modulator includes a differential output driver configured for driving a first and a second output signals in response to the first and the second PWM signals. A clipping detection circuit is configured to turn on a clipping indication signal when one or both of the first PWM signal and the second PWM signal maintain the same state between two consecutive edges of the oscillator clock signal. The clipping detection circuit is also configured to turn off the clipping indication signal when both the first PWM signal and the second PWM signal change states between two consecutive edges of the oscillator clock signal.

主权项

1. An integrated circuit (IC) chip having a class D amplifier for filter-less application, comprising:
an oscillator clock signal having a rising edge and a falling edge in each oscillator clock cycle; a reference ramp voltage generator for generating a reference ramp voltage from the oscillator clock signal; a class-D PWM (pulse width modulation) modulator configured for generating first and second PWM signals in each oscillator clock cycle by comparing first and second complementary input signals with the reference ramp voltage, wherein the first and the second PWM signals are in a first state when the corresponding input signal is higher than the reference ramp voltage, and the first and the second PWM signals are in a second state when the corresponding input signal is lower than the reference ramp voltage; and a clipping detection circuit configured to turn on a clipping indication signal when one or both of the first PWM signal and the second PWM signal maintain the same state between two consecutive edges of the oscillator clock signal, and wherein the clipping detection circuit is configured to turn off the clipping indication signal when both the first PWM signal and the second PWM signal change states between two consecutive edges of the oscillator clock signal.