发明名称 Multi-phase switching regulator and droop circuit therefor
摘要 The present invention provides a multi-phase switching regulator and a droop circuit for use in the multi-phase switching regulator. The multi-phase switching regulator generates pulse width modulation (PWM) signals according to an output voltage and a droop signal, to drive a plurality of switching sets to convert an input voltage to the output voltage. The droop circuit detects the sum of the currents generated by the plurality of switching sets and provides the droop signal which is related to the sum of the currents to the multi-phase switching regulator. The droop signal can be used for over current protection (OCP) or for the droop control.
申请公布号 US8917077(B2) 申请公布日期 2014.12.23
申请号 US201313938154 申请日期 2013.07.09
申请人 Richtek Technology Corporation 发明人 Lin Yu-Ta;Huang Jian-Rong;Wan Yi-Cheng;Wang Chien-Hui;Hsiao Yuan-Wen
分类号 G05F1/00;G05F1/10 主分类号 G05F1/00
代理机构 Tung & Associates 代理人 Tung & Associates
主权项 1. A multi-phase switching regulator, comprising: a plurality of switch sets for generating an output voltage at an output node, wherein each switch set includes at least one power switch and a phase node, and each switch set receives a corresponding driving signal to operate the corresponding at least one power switch thereof for generating the output voltage; a plurality of output inductors, which are coupled between the corresponding phase nodes and the output node respectively; a pulse width modulation (PWM) circuit for generating a plurality of PWM signals to control the plurality of switch sets; and a droop circuit for providing a droop signal, the droop signal being related to a sum of currents through the phase nodes, the droop circuit including: a plurality of phase resistors, which are respectively coupled between the corresponding phase nodes and a common node, and each of which is for sensing a current generated by the corresponding switching set through the corresponding phase node;a droop capacitor, which is coupled between the common node and the output node;a phase buffer circuit, which has a common node terminal coupled to the common node for receiving a common node voltage at the common node, wherein the phase buffer circuit generates a first voltage according to the common node voltage;an output buffer circuit, which has an output node terminal coupled to the output node for receiving the output voltage, wherein the output buffer circuit generates a second voltage according to the output voltage; anda converter circuit, which receives the first voltage and the second voltage and generates the droop signal;wherein there is no substantial current flowing through the common node terminal and the output node terminal.
地址 Chupei, Hsinchu TW