HIGH VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE DEVICES

摘要

Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.

主权项

1. A semiconductor device comprising:
a semiconductor substrate layer of a first conductivity type; optionally, a buffer layer of a semiconductor material of the first conductivity type on the substrate layer; a drift layer of a semiconductor material of the first conductivity type on the buffer layer or on the substrate; a first well region of a semiconductor material of a second conductivity type different than the first conductivity type in the drift layer in a central portion of the device; a second well region of a semiconductor material of the second conductivity type in the drift layer in the central portion of the device and spaced from the first well region; a pillar region of a semiconductor material of the second conductivity type in the drift layer between the first well region and the second well region and spaced from the first well region and the second well region; a first source region of a semiconductor material of the first conductivity in the first well region; a second source region of a semiconductor material of the first conductivity in the second well region; a first gate dielectric layer on the drift layer and in contact with the first source region and the second source region; a gate electrode on a central portion of the first gate dielectric layer, the gate electrode comprising a lower surface on the first gate dielectric layer, an upper surface opposite the lower surface and sidewalls; an interlayer dielectric on the gate electrode and on a peripheral portion of the first gate dielectric layer not covered by the gate electrode; source ohmic contacts on the source regions; and a source metal region in contact with the source ohmic contacts.