发明名称 |
LOW POWER HIGH FREQUENCY DIGITAL PULSE FREQUENCY MODULATOR |
摘要 |
Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output. Described is also a voltage regulator which comprises: mutually coupled on-die inductors for coupling to a load; a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising: a comparator for comparing output voltage of the load with a reference voltage; and a first PDL coupled to the comparator for determining turn-on duration of the high-side switch. |
申请公布号 |
WO2014200461(A1) |
申请公布日期 |
2014.12.18 |
申请号 |
WO2013US45006 |
申请日期 |
2013.06.10 |
申请人 |
THENUS, FENARDI;ZOU, PENG;INTEL CORPORATION;CHEPURI, RAGHU NANDAN;KOERTZEN, HENRY W. |
发明人 |
THENUS, FENARDI;ZOU, PENG;CHEPURI, RAGHU NANDAN;KOERTZEN, HENRY W. |
分类号 |
G05F1/10 |
主分类号 |
G05F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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