发明名称 |
OVER-VOLTAGE TOLERANT CIRCUIT AND METHOD |
摘要 |
Over-voltage tolerant circuits and methods are provided. In one embodiment, the circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias circuit to apply Vcc to a well and gate of the pull-up transistor, a second bias circuit to apply Vpad to the gate and the well of the pull-up transistor, and a non-overlap circuit configured to ensure the gate and the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit. |
申请公布号 |
US2014368960(A1) |
申请公布日期 |
2014.12.18 |
申请号 |
US201314037023 |
申请日期 |
2013.09.25 |
申请人 |
Cypress Semiconductor Corporation |
发明人 |
DEO Supreet Bhanja;WILLIAMS Timothy;MADDEN Pat |
分类号 |
H03K17/08 |
主分类号 |
H03K17/08 |
代理机构 |
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代理人 |
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主权项 |
1. A circuit comprising:
a pull-up transistor coupled to an I/O pad of an electronic device; a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad); a latch coupled to the sensing circuit and configured to retain an output of the sensing circuit; and a selection circuit coupled to the sensing circuit through the latch, the selection circuit comprising:
a first bias circuit to apply Vcc to a well and gate of the pull-up transistor, and a second bias circuit to apply Vpad to the gate and the well of the pull-up transistor; anda non-overlap circuit configured to ensure the gate and the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit. |
地址 |
San Jose CA US |