DUAL-MODE TRANSISTOR DEVICE AND METHOD FOR OPERATING THE SAME

摘要

PROBLEM TO BE SOLVED: To provide a memory structures that supports more efficient operation and low leakage.SOLUTION: A dual-mode transistor structure comprises a semiconductor body 10. The semiconductor body of the device includes a channel region 13, a p-type terminal region 14 (operable as a source or drain) adjacent a first side of the channel region, and an n-type terminal region 15 (operable as a source or drain) adjacent a second side of the channel region. A gate insulator 12 is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate 16A is disposed on a first side of the gate, and a second assist gate 16B is disposed on a second side of the gate. Optionally, a back gate 18 can be included beneath the channel region. Biasing the assist gates can be used to select an n-channel mode or a p-channel mode in a single device.