DECISION CIRCUIT, RECEIVER DEVICE, AND PROCESSOR

摘要

A decision circuit includes: a first decision block to distinguish a first bit of bits using an amplitude of an analog signal as a discrimination point, the analog signal being an amplitude shift keyed signal; a superposition block to acquire an absolute value of a difference of the analog signal in respect to an amplitude center value of the analog signal by superposing divided analog signals; an inversion block to control inverting of the signal based on a first distinction result of the first decision block; a second decision block to distinguish a second bit of the bits based on an amplitude of an output signal from the inversion block and the discrimination point; and an output buffer to output the first distinction result and a second distinction result of the second decision block in synchronization with a clock.

主权项

1. A decision circuit comprising:
a first decision block configured to distinguish a value of a first bit of a plurality of bits by using an amplitude of an analog signal as a discrimination point, the analog signal being an amplitude shift keyed signal in which a demodulation pattern of the plurality of bits is set for each one of a plurality of amplitudes; a superposition block configured to acquire a signal of an absolute value of a difference of the analog signal in respect to an amplitude center value of the analog signal by superposing divided analog signals which is obtained by dividing the analog signal; an inversion block configured to control inverting of the signal based on a first distinction result of the first decision block; a second decision block configured to distinguish a value of a second bit of the plurality of bits based on an amplitude of an output signal from the inversion block and the discrimination point; and an output buffer configured to output the first distinction result and a second distinction result of the second decision block in synchronization with a clock.