METHOD AND APPARATUS FOR CONTROL OF A DIGITAL PHASE LOCKED LOOP (DPLL) WITH EXPONENTIALLY SHAPED DIGITALLY CONTROLLED OSCILLATOR (DCO)

摘要

Various systems and methods utilizing a digitally controlled oscillator having frequency steps that increase in magnitude as a target output clock frequency increases are described. An integrated circuit in accordance with the disclosure includes a plurality of first transistor units fixedly coupled to an input voltage and a plurality of second transistor units switchably coupled to the first transistor units. An output coupled to the plurality of second transistor units and the plurality of first transistor units conveys an output signal having a frequency dependent on which select ones of the second transistor units are enabled. The plurality of second transistor units include a first switchable transistor unit having a transistor of a first width, a second switchable transistor unit having a transistor of a second width greater than the first width, and a third switchable transistor unit having a transistor of a third width greater than the second width.

主权项

1. An integrated circuit comprising:
a plurality of first transistor units fixedly coupled to an input voltage; a plurality of second transistor units switchably coupled to the plurality of first transistor units; and an output electrically coupled to the plurality of second transistor units and the plurality of first transistor units to convey an output signal having a frequency dependent on which select ones of the second transistor units are enabled, wherein an increase in the frequency of the output signal due to a selected one of the second transistor units being enabled is proportional to a width of transistors in the selected one of the second transistor units, wherein the plurality of second transistor units include:
a first switchable transistor unit having at least one transistor of a first width,a second switchable transistor unit having at least one transistor of a second width greater than the first width, anda third switchable transistor unit having at least one transistor of a third width greater than the second width.