METHODS OF FORMING GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING DEVICES

摘要

One illustrative method disclosed herein includes forming gate insulation layers and a first metal layer for NMOS and PMOS devices from the same material, selectively forming a first metal layer only for the PMOS device, and forming different shaped metal silicide regions within the NMOS and PMOS gate cavities. A novel integrated circuit product disclosed herein includes an NMOS transistor with an NMOS gate insulation layer, an NMOS metal silicide having a generally rectangular cross-sectional configuration and an NMOS metal layer positioned on the NMOS metal silicide region. The product also includes a PMOS transistor with the same gate insulation material, a first PMOS metal and a PMOS metal silicide region, wherein the NMOS and PMOS metal silicide regions are comprised of the same metal silicide.

主权项

1. A method of forming replacement gate structures for an NMOS transistor and a PMOS transistor, comprising:
performing at least one etching process to remove a sacrificial gate structure for said NMOS transistor and a sacrificial gate structure for said PMOS transistor to thereby define an NMOS gate cavity and a PMOS gate cavity; depositing a gate insulation layer in said NMOS gate cavity and in said PMOS gate cavity; performing at least one first process operation so as to form a first metal layer on said gate insulation layer in both said NMOS gate cavity and said PMOS gate cavity and thereafter remove said first metal layer within said NMOS gate cavity while leaving a remaining portion of said first metal layer positioned on said gate insulation layer in said PMOS gate cavity; performing at least one second process operation to form first and second metal silicide regions within said NMOS gate cavity and said PMOS gate cavity, respectively, wherein said first metal silicide region is positioned above said gate insulation layer in said NMOS gate cavity and said second metal silicide region is positioned above at least said remaining portion of said first metal layer within said PMOS gate cavity; and forming first and second gate cap layers within said NMOS and PMOS gate cavities, respectively, above said first and second metal silicide regions, respectively.