Enhanced FinFET Process Overlay Mark

摘要

An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

主权项

1. An integrated circuit device comprising:
a substrate having an active device region and an overlay mark region; and a plurality of fins disposed on the substrate within the overlay mark region, each fin of the plurality of fins including a longitudinal body and a fin line-end, wherein the fin line-end defines a reference location for mask overlay analysis to be performed by an overlay metrology system.