EFFICIENT BIT-PLANE DECODING ALGORITHM

摘要

A bitplane decoding system where the bitplane operations are broken up into an optimized plurality of sub-tasks. A pipeline structure is established for the execution of said sub-tasks on a plurality of processors or dedicated hardware logic blocks in a manner that allows efficient execution of the sub-tasks in parallel across two processors, resulting in a significant increase in performance.

主权项

1. A video decoding system comprising a plurality of processors operable to decode an encoded bitplane within a video frame.