发明名称 MULTILAYER CHIP AND FORMATION METHOD OF THE SAME
摘要 PROBLEM TO BE SOLVED: To enhance the yield in a multilayer chip formation method performing the dicing after performing lamination in wafer state. ! SOLUTION: After laminating wafers W1, W2 via a plurality of metal bumps B, the wafers W1, W2 are cut to form a plurality of individualized multilayer chips. When a semiconductor chip DEF having a defect is included in the wafer W1, some of the plurality of metal bumps B, corresponding to the semiconductor chip DEF, are not formed before lamination, and some of electrical connection paths between the semiconductor chip DEF and the corresponding semiconductor chip C of the wafer W2 are interrupted. Since specific semiconductor chips, out of a plurality of semiconductor chips thus laminated, can be disconnected electrically, reduction in the yield can be prevented even if the dicing is performed after performing lamination in wafer state. ! COPYRIGHT: (C)2015,JPO&INPIT
申请公布号 JP2014239143(A) 申请公布日期 2014.12.18
申请号 JP20130120656 申请日期 2013.06.07
申请人 MICRON TECHNOLOGY JAPAN INC 发明人 UCHIYAMA SHIRO
分类号 H01L25/065;H01L25/07;H01L25/18 主分类号 H01L25/065
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