| 摘要 |
A system and device for reducing instantaneous voltage droop (IVD) during a scan shift operation is disclosed. In one embodiment, a system includes a first group of clock gating cells (102A) configured to receive an input clock signal (138) and a first group of flip-flops (104A) coupled to the first group of clock gating cells. Each clock gating cell of the first group of clock gating cells includes a first delay element (116A) to delay the input clock signal by a first duration during a scan shift operation. The system also includes a second group of clock gating cells (102B) configured to receive the input clock signal, and a second group of flip-flops (104B) coupled to the second group of clock gating cells. Each clock gating cell of the second group of clock gating cells includes a second delay element (132A) to delay the input clock signal by a second duration during the scan shift operation. |
