| 摘要 |
Throttle prediction circuit 55 maintains a count of the number of instructions in a sequence between a source branch instruction and a subsequent branch instruction which are both predicted to result in a taken branch by branch prediction circuit 35. The sequence corresponds to instructions fetched by fetch circuit 15 from instruction cache 20. At a subsequent occurrence of the source branch instruction being fetched and predicted to be taken, throttle circuit 55 operates fetch circuit 15 in throttled mode, where the number of instruction retrieved from cache 20 is limited according to said count. Fetching further instructions is prevented for a predetermined number of clock cycles. This way it is avoided to fetch speculative instructions which need to be discarded if a branch is not taken, with no corresponding unnecessary cache accesses. Breaking fetching activity over the predetermined amount of clock cycles is outweighed by reduction in power consumption. |
