| 摘要 |
The invention pertains to a power up test system (600) comprising:
- a first row (Row 1) of ROM memory cells storing a first predetermined data word, each memory cell of the first row (Row 1) of ROM memory cells being connected to corresponding bitlines;
- a second row (Row 2) of ROM memory cells storing a second predetermined data word, each memory cell of the second row (Row 2) of ROM memory cells being connected to the corresponding bitlines, and the second predetermined data word being a single bit shifted first predetermined data word;
- sense amplifiers (606) coupled to the corresponding bitlines for sensing a first read word from the first row (Row 1) of ROM memory cells in a first read operation and for sensing a second read word from the second row (Row 2) of ROM memory cells in a second read operation;
- a dual function data register (608) for receiving the first read word into master latches (662) and for shifting the first read word into slave latches (664) in the first read operation, the dual function data register (608) receiving the second read word into the master latches (662); and
- a data comparison logic for comparing data between the master latches (662) and the slave latches (664), and for providing a signal indicating matching data between the master latches (662) and the slave latches (664). |
