| 发明名称 |
Processor testing |
| 摘要 |
Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution. |
| 申请公布号 |
US8914622(B2) |
申请公布日期 |
2014.12.16 |
| 申请号 |
US201213460413 |
申请日期 |
2012.04.30 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Bansal Abhishek;Gupta Nitin P.;Herold Brad L.;Sankarannair Jayakumar N. |
| 分类号 |
G06F9/32;G06F11/22;G06F9/38;G06F9/30 |
主分类号 |
G06F9/32 |
| 代理机构 |
|
代理人 |
Baudino James L. |
| 主权项 |
1. A method comprising:
randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the first portion branch instructions to the respective instructions being arranged in a sequential manner; randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the second portion branch instructions to the respective instructions being arranged in a sequential manner; generating a plurality of instructions to increment a counter, the counter instructions incrementing the counter when each branch instruction is encountered in the instruction set during execution; and writing the instructions to a computer readable storage medium. |
| 地址 |
Armonk NY US |
