| 主权项 |
1. A multi-port memory cell, comprising:
first and second inverter circuits, each inverter circuit including a pull-up transistor of a first type and a pull-down transistor of a second type; wherein in each inverter circuit:
a gate of the pull-up transistor and a gate of the pull-down transistor are each coupled to a first node and receive the same voltage potential,a source of the pull-up transistor and a drain of the pull-down transistor are coupled in series and provide an inverted output at a second node between the pull-up and pull-down transistors, andthe first node of each inverter circuit is coupled to the second node of the other inverter circuit to receive the inverted output of the other inverter circuit; a first pair of access transistors of the first type, each coupled to the first node of a respective one of the first and second inverter circuits; a second pair of access transistors of the second type, each coupled to the first node of a respective one of the first and second inverter circuits; a substrate; a plurality of well regions in the substrate and extending in parallel in a first direction (y); each of the plurality of well regions having a respective set of fin structures disposed on the region, each fin structure in the respective set extending in the first direction (y); and a plurality of gate structures, each gate structure disposed over one or more of the sets of fin structures and extending in a second direction (x) that is perpendicular to the first direction (y), the fin structures and gate structures configured and arranged to form the FinFETs. |
