Low power quadrature waveform generator

摘要

An apparatus comprising a frequency divider comprising a first latch configured to receive a first clock signal and a complement of the first clock signal and to generate a first latch first output, and a second latch coupled to the first latch in a toggle-flop configuration, a first output circuit comprising a p-channel transistor, wherein the gate of a p-channel transistor is configured to receive the first clock signal, and a n-channel transistor, wherein the drain of the p-channel transistor is directly connected to the drain of a n-channel transistor, wherein the gate of the n-channel transistor is configured to receive the first latch first output, wherein the source of the n-channel transistor is configured to receive the complement of the first clock signal, and wherein the first output circuit is configured to generate an in-phase reference signal, and a second output circuit configured to generate a quadrature signal.

主权项

1. An apparatus comprising:
a frequency divider comprising: a first latch configured to receive a first clock signal and a complement of the first clock signal and to generate a first latch first output; and a second latch coupled to the first latch in a toggle-flop configuration, wherein the second latch is configured to receive the first clock signal and the complement of the first clock signal; a first output circuit comprising: a p-channel transistor, wherein a gate of the p-channel transistor is configured to receive the first clock signal, and wherein a source of the p-channel transistor is configured to receive a voltage supply; and a n-channel transistor, wherein a drain of the p-channel transistor is directly connected to the drain of the n-channel transistor, wherein the gate of the n-channel transistor is configured to receive the first latch first output, and wherein the source of the n-channel transistor is configured to receive the complement of the first clock signal; and a second output circuit configured to receive the first clock signal and the complement of the first clock signal, wherein the first output circuit is configured to generate a first in-phase reference signal and the second output circuit is configured to generate a first quadrature signal.