| 发明名称 | Embedded package structure and method for manufacturing thereof | ||
| 摘要 | The disclosure provides an embedded package structure comprising a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The metal substrate has a first surface and a second surface. The chip module is disposed on the first surface of the metal substrate, and comprises at least two stacked chips being electrically connected to each. The insulation material layer covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection formed therein. The patterned metal layer is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides. | ||
| 申请公布号 | US8912663(B1) | 申请公布日期 | 2014.12.16 |
| 申请号 | US201313930949 | 申请日期 | 2013.06.28 |
| 申请人 | Delta Electronics, Inc. | 发明人 | Lee Chia-Yen;Tsai Hsin-Chang;Lee Peng-Hsin |
| 分类号 | H01L23/52;H01L23/48;H01L23/02;H01L21/50;H01L21/48;H01L21/44;H01L23/00;H01L23/498 | 主分类号 | H01L23/52 |
| 代理机构 | Lowe Hauptman & Ham, LLP | 代理人 | Lowe Hauptman & Ham, LLP |
| 主权项 | 1. An embedded package structure comprising: a metal substrate having a first surface and a second surface; a chip module, disposed on the first surface of the metal substrate, comprising at least two stacked chips being electrically connected to each other; an insulation material layer covering the first surface of the metal substrate and the chip module and having an electrical interconnection formed therein; and at least one patterned metal layer, positioned on the insulation material layer, electrically connected the chip module through the electrical interconnection. | ||
| 地址 | TW | ||