发明名称 Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured space
摘要 Various embodiments identify a design including circuit features and identify an operation that produces an aggressor for victim(s). The operation on the aggressor and the set of victims are implemented using local maximally spanning spacetile(s) while satisfying some design requirements. Where the set of victims includes interconnects, the design may allow no bend in some interconnects. One or more spacetiles are used to perform the operation on the aggressor and implement the interconnects while introducing no bends in the interconnects by using local maximally spanning spacetile(s). Some implementation may perform block modeling for the aggressor to perform the operation on the aggressor and implement a set of victims while preserving the relative order of the interconnects by using the block modeling for the aggressor.
申请公布号 US8914763(B1) 申请公布日期 2014.12.16
申请号 US201213692970 申请日期 2012.12.03
申请人 Cadence Design Systems, Inc. 发明人 Raj Satish;Ananthram Supriya
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Vista IP Law Group, LLP 代理人 Vista IP Law Group, LLP
主权项 1. A computer implemented method for implementing multi-layer local maximal spanning routing paths in an electronic design, comprising: using at least one processor or at least one processor core to perform a process the process comprising: determining a region of interest based at least in part upon one or more requirements and a first feature to be implemented in the region of interest, wherein the one or more requirements includes a design constraint that at least one victim circuit feature in the electronic design needs to satisfy; determining a local, maximally spanning spacetile for the region of interest; and implementing the first circuit feature by using at least the local, maximally spanning spacetile for adjusting the at least one victim circuit feature while satisfying the one or more requirements for the at least one victim circuit feature.
地址 San Jose CA US