Compliant printed circuit wafer probe diagnostic tool

摘要

Diagnostic tools for testing wafer-level IC devices, and a method of making the same. The first diagnostic tool can include a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between distal ends of probe members in the wafer probe and contact pads on a wafer-level IC device. A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location away from the first interface. The electrical devices are electrically coupled to the conductive traces and are configured to provide one or more of continuity testing or functionality of the wafer-level IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a dedicated IC testing device. A plurality of electrical devices are printed on the second compliant printed circuit and electrically coupled to the dedicated IC device.

主权项

1. A diagnostic tool for testing a wafer-level integrated circuit (IC) device coupled to testing electronics, the diagnostic tool comprising:
a first diagnostic tool adapted to be located at a first interface between a wafer probe and the wafer-level IC device, the first diagnostic tool comprising;
a first compliant printed circuit comprising a flexible polymeric sheet with a plurality of contact pads contacting distal ends of probe members in the wafer probe at a first interface and raised probe members located on the compliant printed circuit in an array contacting a plurality of contact pads on the wafer-level IC device at the first interface;a plurality of conductive traces printed on the first compliant printed circuit and electrically coupling to the plurality of contact pads; anda plurality of electrical devices printed on the first compliant printed circuit at a position external to the first interface, the electrical devices coupled to the conductive traces and configured to provide one or more of continuity testing at the first interface or functionality testing of the wafer-level IC device.