System and method of reducing test time via address aware BIST circuitry

摘要

In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.

主权项

1. A method comprising:
initiating a first built-in self-test (BIST) sequence on a plurality of integrated circuit memory arrays having a common BIST control unit; incrementing each address for each said integrated circuit memory array in common from a common starting point, using said common BIST control unit; receiving, by said common BIST control unit from each said integrated circuit memory array, a signal indicating a maximum valid address in said integrated circuit memory array is reached, to receive a plurality of maximum valid addresses; recording, in said common BIST control unit, said maximum valid addresses; determining a single relatively highest maximum valid address from said plurality of maximum valid addresses, using said common BIST control unit; engaging, by said common BIST control unit, a first mode in each said integrated circuit memory array having reached said maximum valid address, said first mode preventing BIST testing; initiating a second BIST sequence from said common BIST control unit on said plurality of integrated circuit memory arrays having said common BIST control unit, based on said common BIST control unit having received said signal indicating a maximum valid address in said integrated circuit memory array is reached from all said integrated circuit memory arrays connected to said common BIST control unit; decrementing an address count from said single relatively highest maximum valid address, using said common BIST control unit; and disengaging, by said common BIST control unit, said first mode for each said integrated circuit memory array as said address count reaches each of said maximum valid addresses of each of said integrated circuit memory arrays during said decrementing.