| 摘要 |
A phase detector (32) for generating a phase difference signal (UP, DOWN) indicative of a phase difference between a first bi-level signal of frequency F1 (Fref) and a second bi-level signal of frequency F2 (Ffb) is proposed. The phase detector may comprise a first detector input (16) for receiving the first bi-level signal, a second detector input (17) for receiving the second bi-level signal, a first flip-flop (4), a second flip-flop (5), a NAND gate (7), a first overphase detection unit (41), and a second overphase detection unit (42). An output of the first overphase detection unit (41) may be connected to a direct input (D) of the second flip-flop (5) and may be arranged to output the level "1" in response to F1 ≤ F2 and the level "0" in response to F1 > F2. An output of the second overphase detection unit (42) may be connected to a direct input (D) of the first flip-flop (4) and may be arranged to output the level "1" in response to F2 ≤ F1 and the level "0" in response to F2 > F1. A sawtooth characteristic of the phase difference signal (UP, DOWN) may thus be avoided. A phase-locked loop comprising the phase detector (32) is also described. |
