LINK AGGREGATOR WITH UNIVERSAL PACKET SCRAMBLER APPARATUS AND METHOD

摘要

Apparatus and methods are presented for using configurable additive data scrambling or descrambling circuitry for multichannel link aggregators in which a scrambler or descrambler polynomial is specified by binary data in a programmable register, and the polynomial data is used to compute a polynomial matrix. A scrambler or descrambler pattern is computed according to the polynomial matrix, and input data is bitwise exclusive-ORed with the computed scrambler or descrambler pattern to generate scrambled or descrambled output data. The scrambling or descrambling circuitry can be reconfigured for different polynomials by reprogramming the register, with the scrambler or descrambler automatically computing an updated polynomial matrix.

主权项

1. A link aggregator apparatus, comprising:
a programmable first electronic register storing binary data representing a scrambler or descrambler polynomial; a matrix generator configured to compute a polynomial matrix at least partially according to the binary data in the first electronic register; and an additive scrambler or descrambler circuit for scrambling or descrambling received current input data, configured to:
compute a next scrambler or descrambler pattern at least partially according to the polynomial matrix and a current scrambler or descrambler pattern, andcompute scrambled or descrambled current output data at least partially according to the next scrambler or descrambler pattern and the current input data.