Receiver Bit Alignment for Multi-Lane Asynchronous High-Speed Data Interface

摘要

The invention uses a PRBS pattern generated by transmitter (serializer) as training At the receiver side, following receiver outputs, a synchronous capturing module is used to capture multiple lanes simultaneously. The captured data is used to calculate the PRBS distance for different lanes. After the distances are obtained, the one with largest latency is used as a reference, to calculate the relative latency with each other lane. This relative latency is further used to calculate the number of shifts for Barrel Shifter and word shifter.

主权项

1. A system comprising:
multiple transmitters each with a pseudorandom binary sequence PRBS generator for providing a training pattern and selection logic for selecting either the training pattern during a training phase or regular data and passing the selection onto serial lanes; and multiple receivers each with a synchronous capturing module for capturing multiple ones of the serial lanes with data simultaneously, the captured data being used to calculate a PRBS distance or bit skew for different lanes, of the distances calculated the distance with the largest latency is used as a reference to calculate a relative latency to other lanes, the relative latency is used to calculate a number of shifts for at least one of a barrel shifter and word shifter in the receiver; wherein the transmitter and receiver cooperate to provide receiver bit alignment for multi-lane asynchronous high speed data interface between the transmitters and receivers.