发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ACCESSING THE SAME |
摘要 |
A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency. |
申请公布号 |
US2014362652(A1) |
申请公布日期 |
2014.12.11 |
申请号 |
US201214355120 |
申请日期 |
2012.03.22 |
申请人 |
Luo Zhijiong;Zhu Zhengyong;Yin Haizhou;Zhu Huilong |
发明人 |
Luo Zhijiong;Zhu Zhengyong;Yin Haizhou;Zhu Huilong |
分类号 |
H01L27/105;H01L29/267;G11C7/00;H01L29/786 |
主分类号 |
H01L27/105 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor memory device, comprising a memory transistor, a first control transistor and a second control transistor,
wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. |
地址 |
Poughkeepsie NY US |