VERTICAL NAND DEVICE WITH LOW CAPACITANCE AND SILICIDED WORD LINES

摘要

A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. Each of the plurality of control gate electrodes includes a first edge surface which is substantially free of silicide, the first edge surface facing the semiconductor channel and the at least one charge storage region and a silicide located on remaining surfaces of the control gate electrode.

主权项

1. A three dimensional memory device, comprising:
a substrate; a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of the substrate; at least one charge storage region located adjacent to semiconductor channel; and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level; wherein each of the plurality of control gate electrodes comprises:
a first edge surface which is substantially free of silicide;the first edge surface facing the semiconductor channel and the at least one charge storage region; anda silicide located on remaining surfaces of the control gate electrode.