Method Of Optimizing Capacitive Couplings In High-Capacitance Nets In Simulation Of Post-Layout Circuits

摘要

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

主权项

1. A method of providing asymmetric asynchronous decoupling of nets in a design for an integrated circuit, the method comprising:
removing a coupling capacitor from an input list, the input list including coupling capacitors in the design, each coupling capacitor capacitively coupling two nets in the design, the two nets having capacitances C1 and C2, at least one of the capacitances C1 and C2 being high, the coupling capacitor having a coupling capacitance Cc; and when the coupling capacitance Cc is low, and only one of the capacitances C1 and C2 is low, then using a forward capacitance at whichever of the two nets has a low capacitance and using a lump capacitance at the other net for simulation.