发明名称 |
INFORMATION PROCESSING SYSTEM |
摘要 |
In an information processing system, plural information processing devices are mutually connected by an SMP connection mechanism. Each of the information processing devices includes a control device (FPGA) having a synchronous register that shows the state of a control signal of the information processing device and an internode communication access control unit that transmits first synchronous packets with the content of the synchronous register reflected to the other information processing devices at predetermined time intervals, receives second synchronous packets from the other information processing devices, and reflects the content of the received second synchronous packets on the synchronous register. |
申请公布号 |
US2014365629(A1) |
申请公布日期 |
2014.12.11 |
申请号 |
US201414295607 |
申请日期 |
2014.06.04 |
申请人 |
Hitachi, Ltd. |
发明人 |
UMEZAWA Akihiro;YAGI Nobuo;SATO Kazuki |
分类号 |
H04L12/24 |
主分类号 |
H04L12/24 |
代理机构 |
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代理人 |
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主权项 |
1. An information processing system in which a plurality of information processing devices are mutually connected by an SMP connection mechanism, each of the information processing devices comprising:
a control device (FPGA) having a synchronous register that shows the state of a control signal of the information processing device and an internode communication access control unit that transmits first synchronous packets with the content of the synchronous register reflected to the other information processing devices of the plurality of information processing devices at predetermined time intervals, receives second synchronous packets from the other information processing devices, and reflects the content of the received second synchronous packets on the synchronous register. |
地址 |
Tokyo JP |