发明名称 |
Method for forming a low resistivity tungsten silicide layer for metal gate stack applications |
摘要 |
Tungsten silicide layers can be used in CMOS transistors in which the work function of the tungsten silicide layers can be tuned for use in PMOS and NMOS devices. A co-sputtering approach can be used in which silicon and tungsten are deposited on a high dielectric constant gate dielectric layer. The tungsten silicide layer can be annealed at or above a critical temperature to optimize the resistivity of the tungsten silicide layer. In some embodiments, the concentration of as-deposited tungsten silicide can be between 50 at % silicon to 80 at % silicon. The critical temperatures can be lower at higher silicon concentration, such as 700 C. at 63 at % silicon to 600 C. at 74 at % silicon. |
申请公布号 |
US2014363942(A1) |
申请公布日期 |
2014.12.11 |
申请号 |
US201313915324 |
申请日期 |
2013.06.11 |
申请人 |
Intermolecular Inc. |
发明人 |
Hong Zhendong;Bodke Ashish;Tzeng Susie |
分类号 |
H01L21/28;H01L29/66 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
1. A method of forming a film stack, the method comprising:
providing a substrate; forming a first layer above the substrate,
wherein the first layer comprises a dielectric material; forming a second layer on the first layer,
wherein the second layer comprises tungsten and silicon; determining a critical temperature for the second layer,
wherein the critical temperature is a temperature at which a rate of change of second layer resistivity over temperature changes observably; and annealing the second layer at a temperature higher than the critical temperature. |
地址 |
San Jose CA US |