发明名称 半導体集積回路
摘要 One embodiment provides a semiconductor integrated circuit, including: a first input wire; a second input wire; a first look-up table (LUT) comprising: a plurality of first memories; a first number of first switches connected to the first input wire; and a second number of second switches connected to the second input wire, the second number being less than the first number, the first LUT being configured to output information which is stored in one of the first memories; and a second LUT including: a plurality of second memories; a third number of third switches connected to the second input wire; and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second LUT being configured to output information which is stored in one of the second memories.
申请公布号 JP5639612(B2) 申请公布日期 2014.12.10
申请号 JP20120072515 申请日期 2012.03.27
申请人 发明人
分类号 H03K19/173 主分类号 H03K19/173
代理机构 代理人
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