| 摘要 |
The present invention relates to a shift register capable of improving a driving ability by preventing a leakage current and reducing a bezel size by reducing the falling edge time of a scan pulse. The shift register includes a plurality of stages which successively output an output pulse composed of a carry pulse and the scan pulse. Among the stages, odd stages successively supply the scan pulses to odd gate lines and even stages successively supply the scan pulses to even gate lines. Each stage includes a carry output unit which generates the carry pulse based on a first discharge voltage and a clock pulse with the same low level voltage as the first discharge voltage and supplies the carry pulse to a front stage or a rear stage, and a scan output unit which generates the scan pulse based on a second discharge voltage which is larger than the first discharge voltage and the clock pulse and supplies the scan pulse to the corresponding gate line. |
