发明名称 導電性構成部品、貫通ビア及び導電性貫通ウェーハ・ビアを含む半導体構成部品を製造するためのプロセス及び集積化スキーム
摘要 <p>A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole is formed in the substrate extending between the first surface and the opposing, second surface. A seed layer is formed on a sidewall defining the at least one hole of the substrate and coated with a conductive layer, and a conductive or nonconductive filler material is introduced into the remaining space within the at least one hole. A method of forming a conductive via through a substrate using a blind hole is also disclosed. Semiconductor components and electronic systems having substrates including the conductive via of the present invention are also disclosed.</p>
申请公布号 JP5639120(B2) 申请公布日期 2014.12.10
申请号 JP20120141907 申请日期 2012.06.25
申请人 发明人
分类号 H01L21/3205;H01L21/768;H01L23/14;H01L23/48;H01L23/522 主分类号 H01L21/3205
代理机构 代理人
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