Semiconductor device

摘要

A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first SRAM cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second SRAM cell. a P-type impurity diffusion region located on a P well between the third gate electrode and the fourth gate electrode located opposite to each other, a first N-type impurity diffusion region located on the side of the third gate electrode closer to the first SRAM cell, and a second N-type impurity diffusion region located on the side of the fourth gate electrode closer to the second SRAM cell.

主权项

1. A semiconductor device comprising:
a first SRAM cell including a first gate electrode group lying in a first direction on a P well and an N well, the first gate electrode group including a first gate electrode constituting an access transistor; a second SRAM cell including a second gate electrode group located symmetrically to the first gate electrode group with respect to an axis in the first direction, the second gate electrode group including a second gate electrode constituting an access transistor; and a first well voltage supply cell located between the first SRAM cell and the second SRAM cell in a direction perpendicular to the first direction and supplying voltages to the P well and the N well, wherein the first well voltage supply cell includes:
a third gate electrode group located symmetrically to the first gate electrode group with respect to a border line with the first SRAM cell located adjacently and including a third gate electrode corresponding to the first gate electrode;a fourth gate electrode group located symmetrically to the second gate electrode group with respect to a border line with the second SRAM cell located adjacently and including a fourth gate electrode corresponding to the second gate electrode;a P-type impurity diffusion region located on the P well between the third gate electrode and the fourth gate electrode located opposite to each other;a first N-type impurity diffusion region located on a side of the third gate electrode closer to the first SRAM cell; anda second N-type impurity diffusion region located on a side of the fourth gate electrode closer to the second SRAM cell.