| 摘要 |
A master stage (502) of a master-slave flip-flop (500) includes an input terminal (504) for receiving the data-in signal, an output terminal, and terminals for receiving first clock signals, a transmission gate (522) coupled to the input terminal and having an output terminal, a storage element (520) coupled to the output terminal of the transmission gate, and a two-input logic gate (525) having a first input terminal (541) coupled to the storage element, a parallel input terminal (542) coupled to the input terminal of the master stage, and an output terminal (543) that provides an output terminal of the master stage. A slave stage (503) has terminals for receiving second clock signals, wherein first clock signals are delayed relative to second clock signals. |
| 主权项 |
1. A parallel master-slave flip-flop (“PMSFF”) having an input terminal for receiving a data-in signal and an output terminal for outputting a data-out signal, comprising:
a master stage comprising an input terminal for receiving the data-in signal, an output terminal, and terminals for receiving first clock signals (MCLK and MCLKB), the master stage configured to latch data at the master stage and to output the data latched at the master stage based on the first clock signals, wherein the master stage includes:
a transmission gate coupled to the input terminal of the master stage, the transmission gate having a control terminal to receive MCLK, another control terminal to receive MCLKB, and an output terminal,a storage element coupled to the output terminal of the transmission gate, wherein the storage element either latches the data-in signal or is transparent, depending on MCLK and MCLKB, anda two-input logic gate having a first input terminal coupled to the storage element, a parallel input terminal coupled to the input terminal of the master stage, and an output terminal that provides an output terminal of the master stage; and a slave stage comprising an input terminal coupled to the output terminal of the master stage, an output terminal for outputting the data-out signal, and terminals for receiving second clock signals (CLK and CLKB), the slave stage configured to latch data at the slave stage and to output the data latched at the slave stage based on the second clock signals. |
