发明名称 |
Gateway apparatus, node apparatus, communication system, control method and computer readable medium |
摘要 |
A gateway apparatus that connects a multi-hop network of tree structure formed of node apparatuses to other network, comprising a grouping unit that groups, for each representative node apparatus having a direct link to the gateway apparatus in the tree structure, the nodes belonging to a subtree having same representative node as a root, into a node group, an interference group specifying unit that specifies a node group in which packet communication in the node group is subjected to an interference of a degree exceeding a threshold as an interference group, and a slot allocation unit that allocates some one time slot among a plurality of time slots included in a frame to one interference group among a plurality of interference groups, and allocates another time slot among the plurality of time slots to another interference group among the plurality of interference groups. |
申请公布号 |
US8908660(B2) |
申请公布日期 |
2014.12.09 |
申请号 |
US201213712744 |
申请日期 |
2012.12.12 |
申请人 |
Fujitsu Limited |
发明人 |
Nagata Nami;Ibuki Jun |
分类号 |
H04B7/212;H04W72/04;H04W28/02;H04W88/16;H04W40/16;H04L12/753;H04W72/08 |
主分类号 |
H04B7/212 |
代理机构 |
Fujitsu Patent Center |
代理人 |
Fujitsu Patent Center |
主权项 |
1. A gateway apparatus that connects a multi-hop network of a tree structure formed of node apparatuses to another network, comprising:
a processor performing a computer program stored in a non-transitory storing medium; a grouping section, implemented using the processor, that groups, for each representative node apparatus having a direct link to the gateway apparatus in the tree structure, the nodes belonging to a subtree having a same representative node as a root, into a node group; an interference group specifying section, implemented using the processor, that specifies a node group in which packet communication in the node group is subjected to an interference of a degree exceeding a threshold as an interference group; and a slot allocation section, implemented using the processor, that allocates one time slot among a plurality of time slots included in a frame which is a packet transmission period of the node apparatus to one interference group among a plurality of interference groups as a packet transmission period, and allocates another time slot among the plurality of time slots to another interference group among the plurality of interference groups as a packet transmission period. |
地址 |
Kawasaki JP |