Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions

摘要

A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.

主权项

1. A memory cell, comprising:
an access device comprising:
a single crystalline semiconductor fin on a substrate extending in a first direction, and separated by insulators from laterally adjacent single crystalline semiconductor fins;a first doped semiconductor region having a first conductivity type in the single crystalline conductive fin; anda polycrystalline member on top of the first doped semiconductor region, the polycrystalline member including a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween;wherein the doping concentration of the second doped semiconductor region is in a range about 10 to about 1000 times higher than the doping concentration of the first doped semiconductor region; an electrode electrically connected to the polycrystalline member; a memory element contacting the electrode; a conductive line extending in a second direction, over and electrically connected to the memory element; and a peripheral area on the substrate including a peripheral circuit single crystal semiconductor region which is part of a single crystal semiconductor body or layer that includes the single crystalline semiconductor fin, the peripheral circuit single crystal semiconductor region including a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the polycrystalline member contacts the first doped semiconductor region without intervening gate dielectric material.