Power clamp for high voltage integrated circuits

摘要

A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.

主权项

1. A device comprising:
a circuit comprising an nMOS device and a pMOS device connected in series between a voltage source terminal and ground; and a trigger unit connected between the voltage source and ground, the trigger unit comprising a plurality of output terminals coupled to respective gates of the nMOS device and pMOS device, the trigger unit responsive to a voltage threshold between the voltage source and ground to apply clamping signals at the output terminals, wherein the voltage source terminal is coupled to ground through the nMOS device and pMOS device; wherein the trigger unit comprises a timing circuit coupled to the voltage source terminal and ground, the timing circuit comprising: a first circuit branch having first capacitive and resistive elements connected between the voltage source terminal and ground, a junction between a first capacitive element and first resistive element connected to the gate of the nMOS device; and a second circuit branch having second capacitive and resistive elements connected between the voltage source terminal and ground, a junction between a second capacitive element and second resistive element connected to the gate of the pMOS device; and wherein the trigger unit further comprises: a first latch circuit directly connected between the junction of the first circuit branch and the gate of the nMOS device; and a second latch circuit directly connected between the junction of the second circuit branch and the gate of the pMOS device.