Processes for forming integrated circuits and integrated circuits formed thereby

摘要

Processes for forming integrated circuits and integrated circuits formed thereby are provided in which a first dielectric layer including a first dielectric material is formed on an underlying substrate. A first etch mask having at least two patterned recesses is patterned over the first dielectric layer. At least one first-level via is etched in the first dielectric layer through one patterned recess in the first etch mask with a first etchant, and the first-level via is filled with electrically-conductive material. A second dielectric layer including a second dielectric material is formed over the first dielectric layer. A second etch mask having patterned recesses corresponding to the patterned recesses of the first etch mask is patterned over the second dielectric layer. Second-level vias are etched in the second dielectric layer through the patterned recesses in the second etch mask with a second etchant and exposed to the first etchant.

主权项

1. A process for forming an integrated circuit, said process comprising:
forming a first dielectric layer on an underlying substrate, the first dielectric layer comprising a first dielectric material; patterning a first etch mask over the first dielectric layer, the first etch mask having at least two patterned recesses; etching at least one first-level via in the first dielectric layer through at least one of the patterned recesses in the first etch mask with a first etchant; filling the at least one first-level via with electrically-conductive material to form a first-level embedded feature within the first dielectric layer; forming a second dielectric layer over the first dielectric layer and the first-level embedded feature therein, the second dielectric layer comprising a second dielectric material different from the first dielectric material wherein the second dielectric material has a lower etch rate in the first etchant than the first dielectric material; patterning a second etch mask over the second dielectric layer, the second etch mask having patterned recesses corresponding to the at least two patterned recesses of the first etch mask; etching second-level vias in the second dielectric layer through the patterned recesses in the second etch mask with a second etchant different from the first etchant; and exposing the second-level vias to the first etchant; wherein etching the second-level vias in the second dielectric layer comprises etching a disconnected second-level via in the second dielectric layer through one of the patterned recesses in the second etch mask, the disconnected second-level via located over an un-etched surface of the first dielectric layer.