Methods for double-patterning-compliant standard cell design

摘要

A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

主权项

1. A semiconductor chip comprising:
a row of cells of a first half-pitch technology, adjacent cells butted together and free of a buffer zone therebetween, with each of the cells comprising:
a plurality of features comprising at least a VDD line and a VSS line;a plurality of first distances each measured between each adjacent pair of the plurality of features;at least one G0 path, each G0 path representing one of the plurality of first distances that is less than a minimum spacing allowed by the first half-pitch technology; andone or more double-patterning full traces comprising one or more G0 paths contiguously traversing from the VDD line to the VSS line; wherein all VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line; and wherein all of the at least one double-patterning full traces in each cell have only an odd number of G0 paths or an even number of G0 paths.