发明名称 Disabling write protection on a serial peripheral interface chip
摘要 Systems and methods for disabling write protection on a serial peripheral interface (SPI) chip are provided. In some aspects, a method includes providing for termination of asserting a hardware write protect pin on the SPI chip by providing for connection of the hardware write protect pin on the SPI chip to a power supply on the SPI chip. The method also includes setting a software write protect enable bit on the SPI chip to indicate that write protection is disabled on the SPI chip. The method also includes reprogramming at least one bit on the SPI chip to a substantially arbitrary value. The at least one bit is different from the hardware write protect pin and the software write protect enable bit.
申请公布号 US8909852(B1) 申请公布日期 2014.12.09
申请号 US201213396376 申请日期 2012.02.14
申请人 Google Inc. 发明人 Kim Yong Jae
分类号 G06F12/00;G06F12/14;G11C16/22;G11C5/00 主分类号 G06F12/00
代理机构 McDermott Will & Emery LLP 代理人 McDermott Will & Emery LLP
主权项 1. A machine-implemented method for disabling write protection on a serial peripheral interface (SPI) chip, the method comprising: providing for termination of asserting a hardware write protect pin on the SPI chip by providing for connection of the hardware write protect pin on the SPI chip to a power supply on the SPI chip, wherein the hardware write protect pin on the SPI chip is connected to a switch, the switch alternating between connecting the hardware write protect pin to a power supply pin of the SPI chip and connecting the hardware write protect pin to a ground pin on the SPI chip, and wherein, upon connecting, using the switch, the hardware write protect pin to the ground pin, the hardware write protect pin is grounded; detecting a status of the hardware write protect pin on the SPI chip via a general purpose input/output (GPIO) pin on the SPI chip, wherein the GPIO pin is connected to the hardware write protect pin; setting a software write protect enable bit on the SPI chip to indicate that write protection is disabled on the SPI chip; and reprogramming at least one bit on the SPI chip to a reprogrammed value, wherein the at least one bit has a different storage location from the hardware write protect pin and the software write protect enable bit.
地址 Mountain View CA US