发明名称 |
Phase locked loop with simultaneous locking to low and high frequency clocks |
摘要 |
A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference. |
申请公布号 |
US8907706(B2) |
申请公布日期 |
2014.12.09 |
申请号 |
US201414263286 |
申请日期 |
2014.04.28 |
申请人 |
Microsemi Semiconductor ULC |
发明人 |
Mitric Krste;Schram Paul;Zargar Tanmay;Colby David;Zhang Cathy;van der Valk Robertus |
分类号 |
H03L7/06;H03L7/10 |
主分类号 |
H03L7/06 |
代理机构 |
Laubscher & Laubscher, P.C. |
代理人 |
Laubscher & Laubscher, P.C. |
主权项 |
1. A method of simultaneously synchronizing a phase-locked loop to high and low frequency clocks, comprising:
(i) locking an output of the phase-locked loop to a high-frequency reference clock; (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop; (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference. |
地址 |
CA |