Content addressable memory (“CAM”)

摘要

A content addressable memory device based on an extremely compact design, potentially as small as 16F2 per memory cell. One embodiment is based on cells having two memory storage elements, such as RRAM elements. Each RRAM element and a respective FET are connected in series between a common matchline and a respective bitline. Cell content for each cell is matched against a bit of a search word by applying voltages to the respective bitlines dependent upon bit value and causing one of the two RRAM elements for each cell to discharge the matchline over a low resistance path in event of mismatch between the cell content and the bit. If no “quick” discharge occurs for multiple cells of a row, then a match is detected. In addition, a matchline recharge path to a high voltage bitline is substantially eliminated by controlling the FETs with specific wordline voltages.

主权项

1. An apparatus comprising a content addressable memory (CAM) cell, the CAM cell comprising:
a first bistable element and a first switch coupled in series between a first bitline and a matchline; a second bistable element and a second switch coupled in series between a second bitline and the matchline; and a control input for the first switch to selectively control a conductance state of the first switch in dependence upon a state of the first bitline; a control input for the second switch to selectively control a conductance state of the second switch in dependence on a state of the second bitline; where the control input for the first switch is to inhibit conduction by the first switch which recharges the matchline, and where the control input for the second switch is to inhibit conduction by the second switch which recharges the matchline.