Erase for 3D non-volatile memory with sequential selection of word lines

摘要

An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.

主权项

1. A method for performing an erase operation for a string of storage elements in a 3D stacked non-volatile memory device, comprising:
pre-charging a channel of the string by applying a pre-charge voltage to one end of the string, the string comprises a plurality of selected storage elements; and subsequently, erasing each selected storage element by applying an erase voltage, higher than the pre-charge voltage, to the one end of the string to charge the channel higher while configuring control gate voltages of the selected storage elements to encourage erasing of the selected storage elements in respective erase periods, wherein a start time of each respective erase period is based on a position of the selected storage element in the string.