Inter-integrated circuit (I2C) multiplexer switching as a function of clock frequency

摘要

In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port.

主权项

1. An inter-integrated circuit (I2C) bus interface comprising:
an I2C master device coupled to an I2C slave device over an I2C bus; and an I2C bus multiplexing circuit coupled to the I2C bus between the I2C master device and the an I2C slave device, wherein the I2C bus multiplexing circuit comprises: a buffer coupled to a signal path from a I2C bus and configured to store an I2C signal from an I2C master device; a frequency detector additionally coupled to the signal path from the I2C bus configured to detect a clock frequency of the I2C signal from the I2C master device; port selection logic coupled to the frequency detector and configured to generate a select control command based on the detected clock frequency; and a multiplexer coupled to the buffer and a plurality of ports, the multiplexer configured to route the I2C signal from the I2C master device to one of the plurality of ports.