发明名称 |
Interrupt controller, apparatus including interrupt controller, and corresponding methods for processing interrupt request event(s) in system including processor(s) |
摘要 |
An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a receiving circuit and a controlling circuit. The receiving circuit receives at least one interrupt input, and the controlling circuit, generates the at least one interrupt request event based on the received at least one interrupt input and routes the at least one interrupt request event generated to the at least one of the processors. The plurality of processors including at least a first processor and a second processor, the first and second processors arranged to process interrupt request event(s), and the controlling circuit is arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor. |
申请公布号 |
US8909836(B2) |
申请公布日期 |
2014.12.09 |
申请号 |
US201213647365 |
申请日期 |
2012.10.08 |
申请人 |
Andes Technology Corporation |
发明人 |
Chen Hsin-Ming;Lai Chi-Chang |
分类号 |
G06F13/24 |
主分类号 |
G06F13/24 |
代理机构 |
|
代理人 |
Hsu Winston;Margo Scott |
主权项 |
1. An interrupt controller, coupled to a plurality of processors, being utilized for routing at least one interrupt request event to at least one of the processors, wherein the interrupt controller comprises:
a receiving circuit, for receiving at least one interrupt input; and a controlling circuit, coupled to the receiving circuit, for generating at least one interrupt request event based on the received interrupt input and routing the interrupt request event generated to at least one of the processors; wherein the plurality of processors includes at least a first processor and a second processor, at least the first and second processors being utilized for processing interrupt request event(s); and the controlling circuit is able to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor. |
地址 |
Science-Based Industrial Park, Hsin-Chu TW |