Bit line resistance compensation

摘要

Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria such as a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a memory plane. Within each zone, different bit line read voltages may be applied to different bit line groupings in order to compensate for systematic variations in bit line resistance between neighboring bit lines due to the use of multiple patterning lithography techniques such as spacer-based double patterning.

主权项

1. A method for compensating for variability in bit line resistance, comprising:
determining a first set of bit line read voltages associated with a zone within a memory plane; determining a second set of bit line read voltages associated with the zone within the memory plane, the first set of bit line read voltages is different from the second set of bit line read voltages; performing a sensing operation on a first set of memory cells and a second set of memory cells within the zone, the performing a sensing operation includes applying the first set of bit line read voltages to the first set of memory cells and applying the second set of bit line read voltages to the second set of memory cells; and outputting data stored in the first set of memory cells and the second set of memory cells based on the performing a sensing operation.