发明名称 |
Systems and methods for determining effective capacitance to facilitate a timing analysis |
摘要 |
A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network. |
申请公布号 |
US8910101(B1) |
申请公布日期 |
2014.12.09 |
申请号 |
US201314051522 |
申请日期 |
2013.10.11 |
申请人 |
Taiwan Semiconductor Manfacturing Co., Ltd. |
发明人 |
Yeh Chao-Yang;Yeh Cheng-Hung;Huang Chi-Ting |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
Duane Morris LLP |
代理人 |
Duane Morris LLP |
主权项 |
1. A method for timing analysis using a processor, comprising:
generating a model that is representative of a coupling between at least two through substrate vias (“TSVs”); determining an impedance profile between the at least two TSVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values; determining an effective capacitance value corresponding to each respective impedance value; populating at least one table with respective impedance values and respective effective capacitance values for each respective frequency value; and conducting an RC extraction of a design layout of a TSV circuit using the populated table and based on each determined effective capacitance value to generate an RC network. |
地址 |
Hsin-Chu TW |